5CEFA5F23I7N Cyclone® V E Field Programmable Gate Array (FPGA) IC 240 5001216 77000 484-BGA

short description:

The Cyclone® V devices are designed to simultaneously accommodate the shrinking power consumption, cost, and time-to-market requirements; and the increasing bandwidth requirements for high-volume and cost-sensitive applications. Enhanced with integrated transceivers and hard memory controllers, the Cyclone V devices are suitable for applications in the industrial, wireless and wireline, military, and automotive markets.

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Product Detail

Product Tags

Product Attributes

TYPE	ILLUSTRATE
category	Field Programmable Gate Arrays (FPGAs)
manufacturer	Intel
series	Cyclone® V E
wrap	tray
Product status	Active
DigiKey is programmable	Not verified
LAB/CLB number	29080
Number of logic elements/units	77000
Total number of RAM bits	5001216
I/O 數	240
Voltage - Power supply	1.07V~1.13V
Installation type	Surface adhesive type
Operating temperature	-40°C ~ 100°C(TJ)
Package/Housing	484-BGA
Vendor component encapsulation	484-FBGA (23x23)
Product master number	5CEFA5

Product Introduction

Product Features

Technology

TSMC's 28-nm low-power (28LP) process technology
1.1 V core voltage

Packaging

Wirebond low-halogen packages
Multiple device densities with compatible package footprints for seamless migration between different device densities
RoHS-compliant and leaded options

High-performance FPGA fabric

Enhanced 8-input ALM with four registers

Internal memory blocks

M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)
Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25% of the ALMs as MLAB memory

Embedded Hard IP blocks

Native support for up to three signal processing precision levels (three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same variable-precision DSP block
64-bit accumulator and cascade
Embedded internal coefficient memory
Preadder/subtractor for improved efficiency
DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support
PCI Express* (PCIe*) Gen2 and Gen1 (x1, x2, or x4) hard IP with multifunction support, endpoint, and root port

Configuration

amper protection—comprehensive design protection to protect your valuable IP investments
Enhanced advanced encryption standard (AES) design security features
CvP
Dynamic reconfiguration of the FPGA
Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and x16 configuration options
Internal scrubbing (2)
Partial reconfiguration (3)