China Manufacturer for Wireless Rf Ic – XC2C256-7TQG144C QFP144 xilinx chips 1.8V Input-output quantity 118 FLASH PLD IC electronic – Yingnuode

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 A complex programmable logic device (CPLD) is a logic device with completely programmable AND/OR arrays and macrocells. Macrocells are the main building blocks of a CPLD, which contain complex logic operations and logic for implementing disjunctive normal form expressions. AND/OR arrays are completely reprogrammable and responsible for performing various logic functions. Macrocells can also be defined as functional blocks responsible for performing sequential or combinatorial logic.

 A complex programmable logic device is an innovative product compared to earlier logic devices like programmable logic arrays (PLAs) and Programmable Array Logic (PAL). The earlier logic devices were not programmable, so the logic was built by combining multiple logic chips together. A CPLD has a complexity between PALs and field-programmable gate arrays (FPGAs). It also has the architectural features of both PALs and FPGAs. The main architectural difference between a CPLD and FPGA is that FPGAs are based on lookup tables, whereas CPLDs are based on sea-of-gates.

The common features of CPLDs and FPGAs are that they both have large numbers of gates and flexible provisions for logic. Whereas common features between CPLDs and PALs include non-volatile configuration memory. CPLDs are leaders in the market of programmable logic devices, having multiple benefits like advanced programming, low cost, being non-volatile and easy to use.

 A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. The main building block of the CPLD is a macrocell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations.

Features[edit]

Some of the CPLD features are in common with PALs:

• Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn’t required, and the CPLD can function immediately on system start-up.
• For many legacy CPLD devices, routing constrains most logic blocks to have input and output signals connected to external pins, reducing opportunities for internal state storage and deeply layered logic. This is usually not a factor for larger CPLDs and newer CPLD product families.

Other features are in common with FPGAs:

• Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.
• Some provisions for logic more flexible than sum-of-product expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly used functions, such as integer arithmetic.

The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD, which allows CPLDs to be used for “boot loader” functions, before handing over control to other devices not having their own permanent program storage. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.^[1]

Distinctions[edit]

CPLDs were an evolutionary step from even smaller devices that preceded them, PLAs (first shipped by Signetics), and PALs. These in turn were preceded by standard logic products, that offered no programmability and were used to build logic functions by physically wiring several standard logic chips (or hundreds of them) together (usually with wiring on a printed circuit board or boards, but sometimes, especially for prototyping, using wire wrap wiring).

The main distinction between FPGA and CPLD device architectures is that CPLDs are internally based on look-up tables (LUTs) while FPGAs use logic blocks.