DS90UB914ATRHSRQ1 Original Brand New QFN DS90UB914ATRHSRQ1 With The Salesman RE-VALIDATE Offer Pleas
Product Attributes
| TYPE | DESCRIPTION | SELECT |
| Category | Integrated Circuits (ICs)
Interface Serializers, Deserializers |
|
| Mfr | Texas Instruments | |
| Series | Automotive, AEC-Q100 | |
| Package | Tape & Reel (TR)
Cut Tape (CT) Digi-Reel® |
|
| Product Status | Active | |
| Function | Deserializer | |
| Data Rate | 1.4Gbps | |
| Input Type | FPD-Link III, LVDS | |
| Output Type | LVCMOS | |
| Number of Inputs | 1 | |
| Number of Outputs | 12 | |
| Voltage - Supply | 1.71V ~ 3.6V | |
| Operating Temperature | -40°C ~ 105°C (TA) | |
| Mounting Type | Surface Mount | |
| Package / Case | 48-WFQFN Exposed Pad | |
| Supplier Device Package | 48-WQFN (7x7) | |
| Base Product Number | DS90UB914 | |
| SPQ | 1000PCS |
A Serializer/Deserializer (SerDes) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. The term "SerDes" generically refers to interfaces used in various technologies and applications. The primary use of a SerDes is to provide data transmission over a single line or a differential pair in order to minimize the number of I/O pins and interconnects.
The basic SerDes function is made up of two functional blocks: the Parallel In Serial Out (PISO) block (aka Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (aka Serial-to-Parallel converter). There are 4 different SerDes architectures: (1) Parallel clock SerDes, (2) Embedded clock SerDes, (3) 8b/10b SerDes, (4) Bit interleaved SerDes.
The PISO (Parallel Input, Serial Output) block typically has a parallel clock input, a set of data input lines, and input data latches. It may use an internal or external phase-locked loop (PLL) to multiply the incoming parallel clock up to the serial frequency. The simplest form of the PISO has a single shift register that receives the parallel data once per parallel clock, and shifts it out at the higher serial clock rate. Implementations may also make use of a double-buffered register to avoid metastability when transferring data between clock domains.
The SIPO (Serial Input, Parallel Output) block typically has a receive clock output, a set of data output lines and output data latches. The receive clock may have been recovered from the data by the serial clock recovery technique. However, SerDes which do not transmit a clock use reference clock to lock the PLL to the correct Tx frequency, avoiding low harmonic frequencies present in the data stream. The SIPO block then divides the incoming clock down to the parallel rate. Implementations typically have two registers connected as a double buffer. One register is used to clock in the serial stream, and the other is used to hold the data for the slower, parallel side.
Some types of SerDes include encoding/decoding blocks. The purpose of this encoding/decoding is typically to place at least statistical bounds on the rate of signal transitions to allow for easier clock recovery in the receiver, to provide framing, and to provide DC balance.
Features for the DS90UB914A-Q1
- Qualified for automotive applications AEC-Q10025-MHz to 100-MHz Input Pixel Clock Support
- Device temperature grade 2: –40℃ to +105℃ ambient operating temperature range
- Device HBM ESD classification level ±8kV
- Device CDM ESD classification level C6
- Programmable data payload:Continuous low latency bidirectional control interface channel with I2C support at 400-kHz
- 10-bit Payload up to 100-MHz
- 12-bit Payload up to 75-MHz
- 2:1 Multiplexer to choose between two input images
- Capable of receiving over 15-m coaxial or 20-m shielded twisted-pair cables
- Robust Power-Over-Coaxial (PoC) operation
- Receive equalizer automatically adapts for changes in cable loss
- LOCK output reporting pin and @SPEED BIST diagnosis feature to validate link integrity
- Single power supply at 1.8-V
- ISO 10605 and IEC 61000-4-2 ESD compliant
- EMI/EMC mitigation with programmable spread spectrum (SSCG) and receiver staggered outputs
Description for the DS90UB914A-Q1
The DS90UB914A-Q1 device offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single coaxial cable or differential pair. The DS90UB914A-Q1 device incorporates differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The deserializer is targeted for connections between imagers and video processors in an ECU (Electronic Control Unit). This device is ideally suited for driving video data requiring up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus.
The deserializer features a multiplexer to allow selection between two input imagers, one active at a time. The primary video transport converts 10-bit or 12-bit data to a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port and is independent of video blanking period.
Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical-bidirectional control channel information. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. In addition, the Deserializer inputs provide adaptive equalization to compensate for loss from the media over longer distances. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects.
