DS90UB936TRGZTQ1 48-VQFN-EP (7×7) integrated circuit 12-BIT 100MHFPD-LINK III DESERIA

1.

FPD-Link-->FPD-LinkII-->FPD-Link III

FPD-Link uses the LVDS standard and has a video data rate of 350Mbit/s on a single twisted pair. 24-bit color data FPD-Link requires the use of 5 twisted pairs.

FPD-LinkII versus FPD-Link, FPD-LinkII uses only one differential pair to transmit clock and video data. LVDS to CML (Current Mode Logic) conversion is used to achieve high data transfer rates - 1.8 Gbit/s.

The main difference between FPD-LINK III (Flat Panel Display Link III) and II is that bi-directional passage is possible on one differential pair and some control signals can be transmitted in addition to video data, thus FPD-Link III reduces even further by eliminating cables for control channels such as I2C and CAN buses. cable costs. discontinuing the use of LVDS technology in favor of CML only for serialized high-speed signals. This makes it easy to work with data rates greater than 3 Gbit / s on cables longer than 10m.

2.

FPD-Link is a high-speed digital video interface primarily used to transmit video data. FPD-link was the first application of the LVDS specification and because FPD-link was the first successful use of LVDS, many display engineers LVDS terminology to replace FPD-link.

The DS90UB948-Q1 is an FPD-Link III deserializer that converts single or dual channel FPD-Link III streams to the FPD-Link (OpenLDI) interface format when used in conjunction with the DS90UB949A/949/947-Q1 serializer.

The deserializer can operate on cost-effective 50Ω single-ended coaxial or 100Ω differential shielded twisted pair (STP) cables.

It can recover data from a single or dual channel FPD-Link III serial stream and then convert it to dual pixel FPD-Link (8 LVDS data channels + clock) supporting up to 2K (2048x1080) video resolution (24-bit color depth).

This provides a bridge between various HDMI-enabled sources (e.g. CPUs) to connect to an existing LVDS display or application processor.

The FPD-Link III interface supports video and audio data transmission and full duplex control (including I2C and SPI communication) over the same differential link.

The integration of video data and control via two differential pairs reduces the size and weight of the interconnects and simplifies system design.

Electromagnetic interference (EMI) is minimized through the use of low-voltage differential signaling, data commutation, and random generation.

In backward-compatible mode, the device supports up to WXGA and 720p resolution (24-bit color depth) on a single differential link.

The device will automatically detect FPD-Link III