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 XC6VLX240T-2FFG1759I FPGAs Overview

The XC6VLX240T-2FFG1759I FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. Using the third-generation ASMBL (Advanced Silicon Modular Block) column-based architecture, the Xilinx XC6VLX240T-2FFG1759I contain many builtin system-level blocks. These features allow logic designers to build the highest levels of performance and functionality into their FPGAbased systems. Built on a 40 nm state-of-the-art copper process technology, XC6VLX240T-2FFG1759I FPGAs are a programmable alternative to custom ASIC technology. offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, connectivity, and soft microprocessor capabilities.

The Xilinx FPGAs (Field Programmable Gate Array) series XC6VLX240T-2FFG1759I is Virtex-6 LXT FPGA 720 I/O 1759FCBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.

Features
Three sub-families:
Virtex-6 LXT FPGAs: High-performance logic with advanced serial connectivity
Virtex-6 SXT FPGAs: Highest signal processing capability with advanced serial connectivity
Virtex-6 HXT FPGAs: Highest bandwidth serial connectivity
Compatibility across sub-families
LXT and SXT devices are footprint compatible in the same package
Advanced, high-performance FPGA Logic
Real 6-input look-up table (LUT) technology
Dual LUT5 (5-input LUT) option
LUT/dual flip-flop pair for applications requiring rich register mix
Improved routing efficiency
64-bit (or two 32-bit) distributed LUT RAM option per 6-input LUT
SRL32/dual SRL16 with registered outputs option
Powerful mixed-mode clock managers (MMCM)
MMCM blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, inputjitter filtering, and phase-matched clock division
36-Kb block RAM/FIFOs
High-performance parallel SelectIO technology
Advanced DSP48E1 slices
Flexible configuration options
SPI and Parallel Flash interface
Multi-bitstream support with dedicated fallback reconfiguration logic
Automatic bus width detection
System Monitor capability on all devices
On-chip/off-chip thermal and supply voltage monitoring
JTAG access to all monitored quantities
Integrated interface blocks for PCI Express designs
GTX transceivers: up to 6.6 Gb/s
Data rates below 480 Mb/s supported by oversampling in FPGA logic.
GTH transceivers: 2.488 Gb/s to beyond 11 Gb/s
Integrated 10/100/1000 Mb/s Ethernet MAC block
Supports 1000BASE-X PCS/PMA and SGMII using GTX transceivers
Supports MII, GMII, and RGMII using SelectIO technology resources
2500Mb/s support available
40 nm copper CMOS process technology
1.0V core voltage (-1, -2, -3 speed grades only)
Lower-power 0.9V core voltage option (-1L speed grade only)
High signal-integrity flip-chip packaging available in standard or Pb-free package options