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XCVU190-2FLGB2104I 100% New & Original Own Stock Integrated Circuit High-Performance Clock Buffer Family

short description:

Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope. High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSI technology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market and application requirements through integration of various system level functions.


Product Detail

Product Tags

Product Attributes

TYPE DESCRIPTION
Category FPGAs (Field Programmable Gate Array)
Mfr AMD
Series Virtex® UltraScale™
Package Tray
Product Status Active
DigiKey Programmable Not Verified
Number of LABs/CLBs 134280
Number of Logic Elements/Cells 2349900
Total RAM Bits 150937600
Number of I/O 702
Voltage - Supply 0.922V ~ 0.979V
Mounting Type Surface Mount
Operating Temperature -40°C ~ 100°C (TJ)
Package / Case 2104-BBGA, FCBGA
Supplier Device Package 2104-FCBGA (47.5x47.5)
Base Product Number XCVU190

Description

Kintex® UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic and next-generation stacked silicon interconnect (SSI) technology. High DSP and block RAM-to-logic ratios and next-generation transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.
Kintex UltraScale+™ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope.
Virtex® UltraScale FPGAs: High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSI technology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market and application requirements through integration of various system level functions.
Virtex UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope.
Zynq® UltraScale+ MPSoCs: Combine the ARM® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application processor with the ARM Cortex-R5 real-time processor and the UltraScale architecture to create the industry's first All Programmable MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration. Zynq® UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leading programmable logic and heterogeneous processing capability.Integrated RF-ADCs, RF-DACs, and soft-decision FECs (SD-FEC) provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.

Summary of Features

RF Data Converter Subsystem Overview
Most Zynq UltraScale+ RFSoCs include an RF data converter subsystem, which contains multiple radio
frequency analog to digital converters (RF-ADCs) and multiple radio frequency digital to analog
converters (RF-DACs). The high-precision, high-speed, power efficient RF-ADCs and RF-DACs can be
individually configured for real data or can be configured in pairs for real and imaginary I/Q data. The
12-bit RF-ADCs support sample rates up to 2GSPS or 4GSPS, depending on the selected device. The 14-bit
RF-DACs support sample rates up to 6.4GSPS.
Soft Decision Forward Error Correction (SD-FEC) Overview
Some Zynq UltraScale+ RFSoCs include highly flexible soft-decision FEC blocks for decoding and encoding
data as a means to control errors in data transmission over unreliable or noisy communication channels.
The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in
5G wireless, backhaul, DOCSIS, and LTE applications.
Processing System Overview
Zynq UltraScale+ MPSoCs and RFSoCs feature dual and quad core variants of the ARM Cortex-A53 (APU)
with dual-core ARM Cortex-R5 (RPU) processing system (PS). Some devices also include a dedicated ARM
Mali™-400 MP2 graphics processing unit (GPU).

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